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FPGA Based Hardware-Software Co-designed Dynamic Binary Translation System


Binary translation is used to allow applications of one instruction set architecture (ISA) to run on another, thereby maintaining the binary level compatibility across ISAs. Conventional software binary translation systems suffer performance loss because of architectural heterogeneity amongst ISAs, control flow translation and context switches. In this paper, we propose an FPGA based hardware-software co-designed dynamic binary translation (DBT) system, which moderates these issues at a low level of hardware cost. In our DBT system, we propose a MIPS condition code flags register and a modest ISA extension to bridge the architectural gap, a hardware address mapping mechanism to accelerate the handling of control flow instructions, and a scratchpad memory to reduce performance loss during context switches.

What is Dynamic Binary Translation

Hardware Supports for DBT (x86 -> MIPS)

Heterogeneity among ISAs

Condition Code Flags (CC-flags)

  • An x86 compatible CC-flags implemented in MIPS, removes the overhead of CC-flag emulation code


  • Little endian -> big endian

  • Modest ISA extension for little endian memory access

LW_LELoad word in little endian
SW_LEStore word in little endian

Control flow translation

To translate branch instructions, the jump target PCs are different from the guest code

  • A hardware Jump-address Lookup Table (JLUT)

Context Switches

Frequent context switches between the DBT and the generated code execution

  • An Scratchpad Memory (SPM) to store the switched out emulated registers

Experiment Result

Performance Improvement

Average speedup by 56.1%, using MiBench benchmarks

Resource Utilization

Occupies extra 1.4% of slices and 5.4% of BRAMs of Xilinx Virtex-5 on-chip resources




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